(1) Field of the Invention
The present invention generally relates to frequency converters that perform dual frequency conversion, and more particularly to frequency converters that down-convert an RF (radio frequency) signal to a baseband frequency. The invention also relates to radio communication devices using such frequency converters.
(2) Description of the Prior Art
FIG. 18 is a block diagram of a known terminal unit such as a wireless LAN (Local Area Network) transceiver. Referring to FIG. 18, the wireless LAN transceiver performs frequency conversion of a signal received via an antenna to obtain an intermediate frequency, and amplifies it. The wireless LAN transceiver then performs AD (analog to digital) conversion of the intermediate frequency and demodulates it to extract a digital signal. The present invention relates to frequency converters that perform this frequency conversion.
Presently, known frequency converters of this kind include those receiving circuits that perform dual frequency conversion (e.g., U.S. Pat. No. 5,448,772). FIG. 19 is a circuit diagram of a frequency converter described in the U.S. Pat. No. 5,448,772 specification.
As shown in FIG. 19, a frequency converter 100 includes an amplifying circuit 50 that is made up of transistors Q1 and Q2 and that amplifies a first signal (RF(+), RF(−)), a switching circuit 51 that performs a first frequency conversion by using a second signal (LO1 (+), LO1 (−)), a switching circuit 52 that performs a second frequency conversion by using a third signal (LO2 (+), LO2 (−)), and a switching circuit 53 that performs a second frequency conversion by using a forth signal (LO3 (+), LO3 (−)). The first switching circuit 51 performs the first frequency conversion and supplies a current signal in a divided manner to the switching circuits 52 and 53, which perform the second frequency conversion. The switching circuits 52 and 53 perform the second frequency conversion and output I and Q baseband signals. The output signals are output after converted into voltage signals by output loads 54.
However, the structure of the U.S. Pat. No. 5,448,772 specification has the following problems. Specifically, the amplifying circuit 50 is operated in a differential manner and thus allows twice as many noises to occur as does an amplifying circuit operated in a single-ended manner. Thus, suppression of the entire noise figure (NF) by using an amplifying circuit that requires high gain causes to increase current fed into the frequency converter.
Additionally, since the frequency of the output signal is in the baseband spectrum, 1/f noise increases. Accordingly, when an optimum amount of current is fed into the switching circuit, the amount of current to be fed into the transistor serving as an amplifying circuit falls short and gain falls short as well, resulting in an increase in the entire NF.
Further, the currents to be fed into the switching circuits 51 to 53 and the amplifying circuit 50 have respective optimum values for obtaining gain, NF, and linearity performance. FIG. 20(A) is a graph showing the current (Isw) flowing through the switching circuits 51 to 53 vs. NF, and the current (Isw) vs. third order input intercept point (IIP3) that is indicative of linearity. FIG. 20(B) is a graph showing the current (Igm) flowing through the amplifying circuit 50 vs. NF, and the current (Igm) vs. third order input intercept point (IIP3) that is indicative of linearity. As shown in FIGS. 20(A) and 20(B), the optimum current value for the amplifying circuit 50 and that for the switching circuits 51 to 53 are different. Additionally, in the patent document 1, the current fed into the switching circuit 51 is the sum of the currents in the switching circuits 52 and 53, which means a current of an optimum value is not necessarily fed into the switching circuit 51.